6.5440 Algorithmic Lower Bounds: Fun with Hardness Proofs (Fall 2023)

Prof. Erik Demaine       TAs: Josh Brunner, Lily Chung, Jenny Diomidova


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[+] Circuit SAT. Dual-rail logic vs. binary logic; Akari/Light Up, Minesweeper (consistency and inference); planar Circuit SAT; Candy Crush / Bejeweled

This lecture starts with a distinction between two key SAT reduction styles:

  • Dual-rail logic: variables + clauses (most proofs we've seen)
  • Binary logic: wires + splitters + clauses (crease pattern proof)
  • Circuit SAT: wires + splitters + universal gates
Then we will see a few proofs in the Circuit SAT style:

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    Handwritten notes, page 1/6[previous page][next page][PDF]
    Video times: • 0:16–7:47

    Handwritten notes, page 1/6[previous page][next page][PDF]

    Slides, page 13/28[previous page][next page][PDF]
    Video times: • 32:55–36:00

    Figures 11 and 12 of http://simon.bailey.at/random/kaye.minesweeper.pdf which in turn is based on http://dx.doi.org/10.1145/1008354.1008356

    Slides, page 13/28[previous page][next page][PDF]