Signals index

Signals

Signals index

ac97_bit_clock : zbt_6111_sample : input
ac97_sdata_in : zbt_6111_sample : input
ac97_sdata_out : zbt_6111_sample : output
ac97_synch : zbt_6111_sample : output
ack : adv7185init : wire

Connects down to:

i2c:i2c:ack

ack : i2c : output reg

Connects up to:

adv7185init:i2c:ack

addr : zbt_6111 : input

Connects up to:

zbt_6111_sample:zbt1:vram_addr

analyzer1_clock : zbt_6111_sample : output
analyzer1_data : zbt_6111_sample : output
analyzer2_clock : zbt_6111_sample : output
analyzer2_data : zbt_6111_sample : output
analyzer3_clock : zbt_6111_sample : output
analyzer3_data : zbt_6111_sample : output
analyzer4_clock : zbt_6111_sample : output
analyzer4_data : zbt_6111_sample : output
audio_reset_b : zbt_6111_sample : output

b : zbt_6111_sample : wire

Connects down to:

delayN:dn3:out

beep : zbt_6111_sample : output
blank : xvga : output reg

Connects up to:

zbt_6111_sample:xvga1:blank

blank : zbt_6111_sample : wire

Connects down to:

xvga:xvga1:blank , delayN:dn3:in

button0 : zbt_6111_sample : input
button1 : zbt_6111_sample : input
button2 : zbt_6111_sample : input
button3 : zbt_6111_sample : input
button_down : zbt_6111_sample : input
button_enter : zbt_6111_sample : input

Connects down to:

debounce:db1:noisy

button_left : zbt_6111_sample : input
button_right : zbt_6111_sample : input
button_up : zbt_6111_sample : input

cb : ntsc_decode : reg
cb_enable : ntsc_decode : wire
cen : zbt_6111 : input
char_index : display_16hex : reg
clean : debounce : output reg

Connects up to:

zbt_6111_sample:db1:user_reset

clk : debounce : input (used in @posedge)

Connects up to:

zbt_6111_sample:db1:clk

clk : delayN : input (used in @posedge)

Connects up to:

zbt_6111_sample:dn1:clk , zbt_6111_sample:dn2:clk , zbt_6111_sample:dn3:clk

clk : ntsc_decode : input (used in @posedge)

Connects up to:

zbt_6111_sample:decode:tv_in_line_clock1

clk : ntsc_to_zbt : input (used in @posedge)

Connects up to:

zbt_6111_sample:n2z:clk

clk : vram_display : input (used in @posedge)

Connects up to:

zbt_6111_sample:vd1:clk

clk : zbt_6111 : input (used in @posedge)

Connects up to:

zbt_6111_sample:zbt1:clk

clk : zbt_6111_sample : wire (used in @posedge)

Connects down to:

SRL16:reset_sr:CLK , debounce:db1:clk , display_16hex:hexdisp1:clock_27mhz , xvga:xvga1:vclock , zbt_6111:zbt1:clk , vram_display:vd1:clk , ntsc_to_zbt:n2z:clk , delayN:dn1:clk , delayN:dn2:clk , delayN:dn3:clk

clk_div_count : adv7185init : reg
clock : display_16hex : wire
clock1 : zbt_6111_sample : input
clock2 : zbt_6111_sample : input
clock4x : i2c : input (used in @posedge)

Connects up to:

adv7185init:i2c:clock_slow

clock_27mhz : adv7185init : input (used in @posedge)

Connects up to:

zbt_6111_sample:adv7185:clock_27mhz

clock_27mhz : display_16hex : input (used in @posedge)

Connects up to:

zbt_6111_sample:hexdisp1:clk

clock_27mhz : zbt_6111_sample : input (used in @posedge)

Connects down to:

DCM:vclk1:CLKIN , adv7185init:adv7185:clock_27mhz

clock_65mhz : zbt_6111_sample : wire

Connects down to:

BUFG:vclk2:O

clock_65mhz_unbuf : zbt_6111_sample : wire

Connects down to:

DCM:vclk1:CLKFX , BUFG:vclk2:I

clock_feedback_in : zbt_6111_sample : input
clock_feedback_out : zbt_6111_sample : output
clock_slow : adv7185init : reg (used in @posedge)

Connects down to:

i2c:i2c:clock4x

clock_tick : display_16hex : wire
col : ntsc_to_zbt : reg
control : display_16hex : reg
count : debounce : reg
count : display_16hex : reg
count : zbt_6111_sample : reg
cr : ntsc_decode : reg
cr_enable : ntsc_decode : wire
current_state : ntsc_decode : reg

Signals

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Created:

Thu Dec 8 21:40:00 2005

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