Prev PageHierarchyFilesModulesSignalsTasksFunctionsHelp
ABCDEFGHIKLMNOPQRSTUVX

Signals index

D
 data : display_16hex : input
Connects up to:fft_sample:d1:dispdata 
 data1 : vga_graph2_buf : input
Connects up to:fft_sample:vg1:gdat1 
 data2 : vga_graph2_buf : input
Connects up to:fft_sample:vg1:gdat2 
 daughtercard : fft_sample : inout
 dclk : vga_graph2_buf : input
Connects up to:fft_sample:vg1:clk_dsp 
 dcount : fft_sample : reg
 delay : adc_driver : reg
 dispdata : fft_sample : wire
Connects down to:display_16hex:d1:data 
 dispflag : vga_graph2_buf : wire
 disp_blank : display_16hex : output
Connects up to:fft_sample:d1:disp_blank 
 disp_blank : fft_sample : output
Connects down to:display_16hex:d1:disp_blank 
 disp_ce_b : display_16hex : output reg
Connects up to:fft_sample:d1:disp_ce_b 
 disp_ce_b : fft_sample : output
Connects down to:display_16hex:d1:disp_ce_b 
 disp_clock : display_16hex : output
Connects up to:fft_sample:d1:disp_clock 
 disp_clock : fft_sample : output
Connects down to:display_16hex:d1:disp_clock 
 disp_data_in : fft_sample : input
 disp_data_out : display_16hex : output reg
Connects up to:fft_sample:d1:disp_data_out 
 disp_data_out : fft_sample : output
Connects down to:display_16hex:d1:disp_data_out 
 disp_reset_b : display_16hex : output reg
Connects up to:fft_sample:d1:disp_reset_b 
 disp_reset_b : fft_sample : output
Connects down to:display_16hex:d1:disp_reset_b 
 disp_rs : display_16hex : output reg
Connects up to:fft_sample:d1:disp_rs 
 disp_rs : fft_sample : output
Connects down to:display_16hex:d1:disp_rs 
 done : fft_256pt_8bit : output
Connects down to:XFFT_V3_1:inst:DONE 
Connects up to:fft_sample:fft1:fft_done 
 dots : display_16hex : reg
 dot_index : display_16hex : reg
 dreset : display_16hex : wire
 dstart : vga_graph2_buf : input
Connects up to:fft_sample:vg1:fft_done 
 dv : fft_256pt_8bit : output
Connects down to:XFFT_V3_1:inst:DV 
Connects up to:fft_sample:fft1:fft_dv 
E
 edone : fft_256pt_8bit : output
Connects down to:XFFT_V3_1:inst:EDONE 
Connects up to:fft_sample:fft1:fft_edone 
 en : vga_sync : wire
 end_buf : vga_graph2_buf : wire
F
 fft_busy : fft_sample : wire
Connects down to:fft_256pt_8bit:fft1:busy 
 fft_ce : fft_sample : wire
Connects down to:fft_256pt_8bit:fft1:ce 
 fft_done : fft_sample : wire
Connects down to:fft_256pt_8bit:fft1:done , vga_graph2_buf:vg1:dstart 
 fft_dv : fft_sample : wire
Connects down to:fft_256pt_8bit:fft1:dv 
 fft_edone : fft_sample : wire
Connects down to:fft_256pt_8bit:fft1:edone 
 fft_out_sum_sq : fft_sample : wire
 fft_rfd : fft_sample : wire
Connects down to:fft_256pt_8bit:fft1:rfd 
 fft_start : fft_sample : wire
Connects down to:fft_256pt_8bit:fft1:start 
 flash_address : fft_sample : output
 flash_byte_b : fft_sample : output
 flash_ce_b : fft_sample : output
 flash_data : fft_sample : inout
 flash_oe_b : fft_sample : output
 flash_reset_b : fft_sample : output
 flash_sts : fft_sample : input
 flash_we_b : fft_sample : output
 fpixel : fft_sample : wire
 frame_over : vga_graph2_buf : wire
 fwd_inv : fft_256pt_8bit : input
Connects down to:XFFT_V3_1:inst:FWD_INV 
Connects up to:fft_sample:fft1:fwd_inv 
 fwd_inv : fft_sample : wire
Connects down to:fft_256pt_8bit:fft1:fwd_inv 
 fwd_inv_we : fft_256pt_8bit : input
Connects down to:XFFT_V3_1:inst:FWD_INV_WE 
Connects up to:fft_sample:fft1:fwd_inv_we 
 fwd_inv_we : fft_sample : wire
Connects down to:fft_256pt_8bit:fft1:fwd_inv_we 
ABCDEFGHIKLMNOPQRSTUVX
Next PageHierarchyFilesModulesSignalsTasksFunctionsHelp
This page: Created:Thu Dec 8 21:40:41 2005
Verilog converted to html by v2html 7.30 (written by Costas Calamvokis).Help