Signals index

Signals

Signals index

a : math_8bit_mult : input

Connects down to:	MULT_GEN_V7_0:inst:A
Connects up to:	fft_sample:m8m_signed2:xk_im , fft_sample:m8m_signed1:xk_re

ac97_bit_clock : fft_sample : input
ac97_sdata_in : fft_sample : input
ac97_sdata_out : fft_sample : output
ac97_synch : fft_sample : output
adc_clk : adc_driver : output wire

Connects up to:

fft_sample:ad1:adc_clk

adc_clk : fft_sample : wire

Connects down to:

adc_driver:ad1:adc_clk

adc_cs_b : adc_driver : output wire

Connects up to:

fft_sample:ad1:adc_cs_b

adc_cs_b : fft_sample : wire

Connects down to:

adc_driver:ad1:adc_cs_b

adc_data0 : adc_driver : input

Connects up to:

fft_sample:ad1:adc_data0

adc_data0 : fft_sample : wire

Connects down to:

adc_driver:ad1:adc_data0

adc_data1 : adc_driver : input

Connects up to:

fft_sample:ad1:adc_data1

adc_data1 : fft_sample : wire

Connects down to:

adc_driver:ad1:adc_data1

adc_rdy : fft_sample : wire

Connects down to:

adc_driver:ad1:rdy

adc_scale : fft_sample : wire
adc_v0 : fft_sample : wire

Connects down to:

adc_driver:ad1:v0

adc_v1 : fft_sample : wire

Connects down to:

adc_driver:ad1:v1

analyzer1_clock : fft_sample : output
analyzer1_data : fft_sample : output
analyzer2_clock : fft_sample : output
analyzer2_data : fft_sample : output
analyzer3_clock : fft_sample : output
analyzer3_data : fft_sample : output
analyzer4_clock : fft_sample : output
analyzer4_data : fft_sample : output
audio_reset_b : fft_sample : output

b : math_8bit_mult : input

Connects down to:	MULT_GEN_V7_0:inst:B
Connects up to:	fft_sample:m8m_signed2:xk_im , fft_sample:m8m_signed1:xk_re

beep : fft_sample : output
blank : fft_sample : wire

Connects down to:

vga_sync:vga1:blank

blank : vga_sync : output wire

Connects up to:

fft_sample:vga1:blank

bpix : vga_graph2_buf : wire
bpixfl : vga_graph2_buf : wire
buf_cnt : vga_graph2_buf : reg
busy : fft_256pt_8bit : output

Connects down to:	XFFT_V3_1:inst:BUSY
Connects up to:	fft_sample:fft1:fft_busy

button0 : fft_sample : input
button1 : fft_sample : input
button2 : fft_sample : input
button3 : fft_sample : input
button_down : fft_sample : input
button_enter : fft_sample : input

Connects down to:

debounce:dbreset:noisy

button_left : fft_sample : input
button_right : fft_sample : input
button_up : fft_sample : input

ce : fft_256pt_8bit : input

Connects down to:	XFFT_V3_1:inst:CE
Connects up to:	fft_sample:fft1:fft_ce

char_index : display_16hex : reg
clean : debounce : output reg

Connects up to:

fft_sample:dbreset:user_reset

clk : adc_driver : input (used in @posedge)

Connects up to:

fft_sample:ad1:clk

clk : debounce : input (used in @posedge)

Connects up to:

fft_sample:dbreset:clk

clk : fft_256pt_8bit : input

Connects down to:	XFFT_V3_1:inst:CLK
Connects up to:	fft_sample:fft1:clk

clk : fft_sample : wire (used in @posedge)

Connects down to:

SRL16:reset_sr:CLK , debounce:dbreset:clk , adc_driver:ad1:clk , fft_256pt_8bit:fft1:clk , math_8bit_mult:m8m_signed1:clk , math_8bit_mult:m8m_signed2:clk , vga_sync:vga1:clk , vga_graph2_buf:vg1:vclock , display_16hex:d1:clock_27mhz

clk : math_8bit_mult : input

Connects down to:	MULT_GEN_V7_0:inst:CLK
Connects up to:	fft_sample:m8m_signed1:clk , fft_sample:m8m_signed2:clk

clk : vga_sync : input (used in @posedge)

Connects up to:

fft_sample:vga1:clk

clk_dsp : fft_sample : wire

Connects down to:

vga_graph2_buf:vg1:dclk

clock : display_16hex : reg (used in @posedge)
clock1 : fft_sample : input
clock2 : fft_sample : input
clock_27mhz : display_16hex : input (used in @posedge)

Connects up to:

fft_sample:d1:clk

clock_27mhz : fft_sample : input

Connects down to:

DCM:vclk1:CLKIN

clock_50MHz : fft_sample : wire

Connects down to:

BUFG:vclk2:O

clock_50mhz_unbuf : fft_sample : wire

Connects down to:

DCM:vclk1:CLKFX , BUFG:vclk2:I

clock_feedback_in : fft_sample : input
clock_feedback_out : fft_sample : output
control : display_16hex : reg
copy_done : vga_graph2_buf : wire
copy_flag : vga_graph2_buf : wire
count : adc_driver : reg
count : debounce : reg
count : display_16hex : reg
cp_cnt : vga_graph2_buf : reg
cumpix : fft_sample : wire
cx : vga_graph2_buf : input
cy : vga_graph2_buf : input

Signals

This page:

Created:

Thu Dec 8 21:40:41 2005

Verilog converted to html by v2html 7.30 (written by Costas Calamvokis).

Help