Prev PageHierarchyFilesModulesSignalsTasksFunctionsHelp
ABCDFIJKLMNOPRSTUVWX

Signals index

S
 SINE : dds_20bit : output
Connects up to:filter_sample:dds1:sine 
 sine : filter_sample : wire
Connects down to:dds_20bit:dds1:SINE 
 source : ac97commands : input
Connects up to:audio:cmds:source 
 source : audio : wire
Connects down to:ac97commands:cmds:source 
 state : ac97commands : reg
 state : display_16hex : reg
 state : filter_sample : wire
Connects down to:jtag2mem:j2m:ctrl_state 
 switch : filter_sample : input
 systemace_address : filter_sample : output
 systemace_ce_b : filter_sample : output
 systemace_data : filter_sample : inout
 systemace_irq : filter_sample : input
 systemace_mpbrdy : filter_sample : input
 systemace_oe_b : filter_sample : output
 systemace_we_b : filter_sample : output
T
 the_ctrl : jtag2mem : wire
 the_data : jtag2mem : wire
 the_we : jtag2mem : wire
 to_ac97_data : filter_sample : wire
Connects down to:audio:myaudio:audio_out_data 
 tv_in_aef : filter_sample : input
 tv_in_aff : filter_sample : input
 tv_in_clock : filter_sample : output
 tv_in_data_valid : filter_sample : input
 tv_in_fifo_clock : filter_sample : output
 tv_in_fifo_read : filter_sample : output
 tv_in_hff : filter_sample : input
 tv_in_i2c_clock : filter_sample : output
 tv_in_i2c_data : filter_sample : inout
 tv_in_iso : filter_sample : output
 tv_in_line_clock1 : filter_sample : input
 tv_in_line_clock2 : filter_sample : input
 tv_in_reset_b : filter_sample : output
 tv_in_ycrcb : filter_sample : input
 tv_out_blank_b : filter_sample : output
 tv_out_clock : filter_sample : output
 tv_out_hsync_b : filter_sample : output
 tv_out_i2c_clock : filter_sample : output
 tv_out_i2c_data : filter_sample : output
 tv_out_pal_ntsc : filter_sample : output
 tv_out_reset_b : filter_sample : output
 tv_out_subcar_reset : filter_sample : output
 tv_out_vsync_b : filter_sample : output
 tv_out_ycrcb : filter_sample : output
U
 up : user_updown3 : wire
Connects down to:debounce:dbu:clean 
 user1 : filter_sample : inout
 user2 : filter_sample : inout
 user3 : filter_sample : inout
 user4 : filter_sample : inout
 user_reset : filter_sample : wire
Connects down to:debounce:dbreset:clean 
V
 vga_out_blank_b : filter_sample : output
 vga_out_blue : filter_sample : output
 vga_out_green : filter_sample : output
 vga_out_hsync : filter_sample : output
 vga_out_pixel_clock : filter_sample : output
 vga_out_red : filter_sample : output
 vga_out_sync_b : filter_sample : output
 vga_out_vsync : filter_sample : output
 vol : ac97commands : wire
 volume : ac97commands : input
Connects up to:audio:cmds:volume 
 volume : audio : wire
Connects down to:ac97commands:cmds:volume 
ABCDFIJKLMNOPRSTUVWX
Next PageHierarchyFilesModulesSignalsTasksFunctionsHelp
This page: Created:Sun Dec 11 13:11:05 2005
Verilog converted to html by v2html 7.30 (written by Costas Calamvokis).Help