| Week of |
Tue |
Thu |
| Sep 01 |
Registration Day |
L01: Course overview. Digital abstraction, static discipline, logic families
|
| Sep 08 |
L02: Combinational logic, canonical representations, simplification and synthesis
|
L03: Verilog hardware description languge. FPGA architectures
|
| Sep 15 |
L04: Sequential building blocks, state and feedback, registers
|
L05: Finite state machines, Verilog implementation examples
|
| Sep 22 |
L06: CI-M requirements. Clocking, synchronization and metastability
|
L07: Memories: on-chip, SRAM, DRAM, Flash
|
| Sep 29 |
L08: Number representations, adders, improving latency
|
L09: Multipliers, behavioral transformations
|
| Oct 06 |
L10: Analog building blocks (opamps, DACs, ADCs), sampling, reconstruction, filtering.
|
L11: Project kickoff
|
| Oct 13 |
L12: Case study: video circuits
|
"Lecture Holiday" (no lecture)
come work on Lab #4!
|
| Oct 20 |
L13: Datapaths and control logic, microsequencers, programmable components
|
L14: Case study: communication links
|
| Oct 27 |
Project Abstract due
|
Writing workshop (attendance required)
| Project Proposal Meeting before 10/31 @ 5pm |
|
| Nov 03 |
Project Block Diagram Meeting before 11/7 @ 5pm
| Lab #3 Revised Report due 11/7 @ 5pm |
|
| Nov 10 |
Project Design Presentations (Wed, Thu)
Project Checklist due 11/14 @ 5p
|
| Nov 17 |
|
| Nov 24 |
|
Thanksgiving |
| Dec 01 |
|
| Dec 08 |
Project Demos and videotaping (Mon, Tue, Wed)
Project Report due 12/10 @ 5pm
|
|