6.111 Handouts

Lectures	L01: Digital Abstraction, 9/5/07 [PDF] L02: Logic Gates, 9/7/07 [PDF] L03: Logic Synthesis, 9/10/07 [PDF] L04: Introduction to Verilog, 9/12/07 [PDF] L05: Sequential Logic, 9/14/07 [PDF] L06: FSMs, 9/17/07 [PDF] L07: FSM examples, 9/19/07 [PDF L08: System Integration Issues, 9/26/07 [PDF] L09: On-chip memories, 9/28/07 [PDF \| CI-M slides \| fifo.v ] L10: Memories, 10/1/07 [PDF] L11: Analog Building Blocks, 10/3/07 [PDF] L12: Arithmetic: Addition & Subtraction, 10/10/07 [PDF] L13: Arithmetic: Multiplication & Transformations, 10/12/07 [PDF] L14: Lab 4 & Final Project, 10/15/07 [PDF] L15: Video Circuits, 10/17/06 [PDF] L16: Potpourri, 10/22/07 [PDF \| fft.v] L17: FSMs++, FPGAs @ home, 10/24/07 [PDF \| beta2.pdf \| beta.v ]

Labs	Lab #1, checkoff deadline: 5pm, 9/14/07 [HTML], Lab 1 Report Template [PDF] Lab #2, checkoff deadline: 5pm, 9/21/07 [HTML] Lab #3, checkoff deadline: 5pm, 10/5/07 [HTML] Lab #4, checkoff deadline: 5pm, 10/19/07 [HTML] Lab #5, checkoff deadline: 5pm, 10/26/07 [HTML]

Final Project	Information and Schedule [HTML] How to Make your 6.111 Project Work [HTML]

Practice Midterm	Fall06: test [PDF], solutions [PDF]

Info	Information Form [PDF] Safety Memo [PDF] Kit signout form [PDF] On-line Verilog HDL Quick Reference Guide The IEEE Verilog 1364-2001 Standard. What's News, and Why You Need It Parameterized Models Using Verilog 2001 Synthesizable Verilog Programming Conventions and Resources Quick Start Guide to the Logic Analyzer [HTML] The XYZ's of Logic Analyzers [PDF] Report guide [HTML] The Mayfield Handbook of Technical and Scientific Writing Writing Guidelines for Engineering and Science Students (see the Design Reports section)

Data sheets	Texas Instruments Digital Logic Pocket Data Book [PDF] Pin Assignment Diagrams [PDF]