Week of	Mon	Wed	Fri
Sep 04	Labor Day	L01: The digital abstraction, static discipline	L02: Combinational logic gates, logic families
Sep 11	L03: Canonical logic representations, simplification and synthesis.	L04: Verilog hardware description language	L05: Sequential building blocks, state and feedback, latches, registers Lab #1 checkoff by 5pm
Sep 18	L06: Finite state machines, metastability and synchronization	L07: FSM example using FPGA and lab kit	Lab #2 checkoff by 5pm
Sep 25	Student Holiday	L08: System integration issues	L09: CI-M Requirements, On-chip Memories
Oct 02	L10: External memories: SRAM, FLASH, DRAM	L11: Analog building blocks	Lab #3 checkoff by 5pm
Oct 09	Columbus Day	L12: Arithmetic circuits: adders, carry lookahead Lab #3 report due by 5pm	L13: Arithmetic circuits: multipliers, behavioral transformations
Oct 16	L14: Project Kickoff	L15: Case study: Video circuits	Lab #4 checkoff by 5pm
Oct 23	L16: Case study: digital signal processing Project Teams due	L17: Case study: Architecture to Verilog, an extended example. Last lecture.	Lab #5 checkoff by 5pm
Oct 30	Project Abstract due Lab #3 Revised Report by 5pm	Evening Quiz 7:30 - 9:30, 50-340	Project Proposal Conf. w/ staff
Nov 06			Veteran's Day Project Block Diagram Conf. w/ staff
Nov 13	Project Design Presentations (M, Tu, W)
Nov 20		Project Checklist due	Thanksgiving
Nov 27
Dec 04
Dec 11	Project Demos and videotaping (Mon & Tue)	Project Demos and videotaping Project Report by 5pm

Last modified on 7/15/06