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Hierarchy
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Hierarchy for dds_sample
dds_sample
BUFG
SRL16
audio
ac97
ac97commands
dds_8bit
C_ADDSUB_V7_0 x 5
C_DIST_MEM_V7_0 x 2
C_GATE_BIT_V7_0 x 5
C_REG_FD_V7_0 x 3
C_SHIFT_FD_V7_0 x 6
LUT4 x 3
debounce
display_16hex
tone750hz
user_updown3
debounce
x 2
Hierarchy
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This page:
Created:
Thu Dec 8 21:42:35 2005
Verilog converted to html by
v2html 7.30
(written by
Costas Calamvokis
).
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