- MW 10-11:30am
- MIT - 9-057
· Class List
Theory of Parallel Hardware
This class covers mathematical foundations of parallel hardware, from
computer arithmetic to physical design, focusing on algorithmic
underpinnings. Topics include arithmetic circuits, parallel prefix,
systolic arrays, retiming, clocking methodologies, boolean logic,
sorting networks, interconnection networks, hypercubic networks,
P-completeness, VLSI layout theory, reconfigurable wiring, fat-trees,
and area-time complexity.
The class is suitable for both theory and systems students. M.Eng.
students can use the class to satisfy their Engineering Concentration
in either Theoretical Computer Science or Computer Systems and
If you expect to register for this class, please send
email as soon as possible so that the course staff
can plan resources appropriately.
- Credit: 3-0-9 H-level Graduate Credit
- Prerequisites: 6.046J (algorithms) and 6.004
(computation structures), or equivalent
- Prof. Charles E. Leiserson, MIT EECS and CSAIL
- Prof. Michael Bender, SUNY, Stony Brook
- Dr. Bradley Kuszmaul, MIT CSAIL
The 6.896 final examination will be administered in class from 10:00
A.M. to 11:30 A.M. on Wednesday, May 12, 2004. All students will be allowed
two 8.5"x11" sheets of handwritten notes
during this closed-book exam. The exam will cover all topics of the
course and test for understanding of material rather than in-depth
problem solving. Students will be expected to solve problems
reasonable for a one and a half hour final. A problem session will be
held in class on Monday, May 10, to review problem-set solutions for the
second half of the course.
Optionally, students may choose to take the exam on Wednesday, May 19th,
at 9:00 A.M. in Walker. Students who wish to take this option should inform
the TA A.S.A.P.