Week of	Mon	Wed	Fri
Sep 06	Labor Day	L01: The digital abstraction, static discipline	L02: Combinational logic gates, logic families
Sep 13	L03: Canonical logic representations, simplification and synthesis.	L04: Verilog hardware description language	L05: Sequential building blocks, state and feedback, latches, registers
Sep 20	L06: Finite state machines, metastability and synchronization	L07: FSM example using FPGA and lab kit	Lab 1 checkoff by 5pm schedule w/ TA
Sep 27	L08: CI-M requirements. Memories	L09: Arithmetic circuits: adders, carry lookahead	Quiz #1
Oct 04	L10: Arithmetic circuits: multipliers, behavioral transformations	L11: Analog building blocks	Lab 2 checkoff by 5pm schedule w/ TA
Oct 11	Columbus Day	L12: System integration, Lab 3 design discussion Lab 2 report due (in class)	L13: Reconfigurable logic
Oct 18	L14: Project Kickoff	L15: Project Management	Lab 3 analog checkoff by 5pm schedule w/ TA
Oct 25	L16: Case study: Architecture to Verilog, an extended example. Project Teams due	L17: Case study: Video circuits	Lab 3 checkoff & report by 5pm schedule w/ TA
Nov 01	Project Abstract due	Lab 2 revised report due 5pm @ 32-G886	Project Proposal Conf. schedule w/ TA
Nov 08			Project Block Diagram Conf. schedule w/ TA
Nov 15		Project Design Presentations everyone must attend Project Checklist Due	Project Design Presentations everyone must attend
Nov 22	Project Design Presentations everyone must attend		Thanksgiving
Nov 29
Dec 06	Project Demos and videotaping (Mon & Tue)	Project Report Due 5pm @ 32-G886

Last modified on 8/7/04